Differential bipolar stray-insensitive pipelined digital-to-analog converter

ABSTRACT

A pipelined digital-to-analog converter (DAC) converts a digital input to an analog output. The pipelined DAC has a plurality of stages. A first of the plurality of stages is coupled to an initialization capacitor and ground. Each of the remainder of the plurality of stages is coupled to a respective previous stage. Each of the plurality of stages includes a capacitor, a first switch and a second switch. The capacitor has first and second plates. The capacitor receives a charge at the first plate in accordance with an associated bit of the digital input. The first switch couples the first plate of the capacitor to ground when the capacitor is not receiving the charge. The second switch couples the second plate of the capacitor to ground when the capacitor is receiving the charge. Coupling the capacitor to ground reduces the effect of stray capacitance in the pipelined DAC, improving its performance.

CROSS-REFERENCES TO RELATED APPLICATIONS

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STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSOREDRESEARCH OR DEVELOPMENT

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REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAMLISTING APPENDIX SUBMITTED ON A COMPACT DISK

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BACKGROUND OF THE INVENTION

A digital-to-analog converter (DAC) is a device for generating an analogoutput (usually a voltage or current) that is a representation of asequence of bits at its input. For example, an 8-bit DAC outputs avoltage or current that can have one of 256 different values. So if theoutput ranges from 0 to 10V, the DAC outputs a voltage corresponding toone of 256 voltage levels between 0 and 10V. A number of techniques areused to implement this conversion.

One such technique is known as an algorithmic DAC, which is based on astep-by-step method. Generally, a multi-bit word, or digital input, isprocessed one portion at a time. In each step, a partial result from theprevious step is combined with a portion of the multi-bit input word andthen passed on to the next step.

FIG. 1 is a flowchart illustrating the steps involved in the basicalgorithmic DAC. The input word is processed one bit at a time, startingfrom the least significant bit. An interim value R is initialized tozero. A counter n, used to count the number of bits processed, is alsoinitialized to zero. A loop commences wherein if a bit b_(n) is 0, theinterim value R is divided in half. If the bit b_(n) is 1, the sum ofthe interim value R and a reference voltage V_(ref) is divided in half.The value of the counter n is increased by one. The loop is repeated forthe next-most significant bit until n=N, where N is the total number ofbits in the word input. At that point, the interim value R represents ananalog form of the word input. Dividing R in half weights the digitalbits according to their significance. That is, the least significant bithas the smallest impact on the outcome of the DAC since it will bedivided more times than any of the other bits.

Although there are other algorithms available in the art, the abovetechnique is attractive because of the savings it offers in terms ofcircuit size and power. Two architectures that have been developed toimplement this technique are the pipelined DAC and the cyclic DAC. Thepipelined DAC provides operating speed at the expense of size and,therefore, power. The cyclic DAC is more economical than the pipelinedDAC since it reuses the same hardware for each iteration of thealgorithm. However, the reduction in size of the cyclic DAC comes at theexpense of a lower output rate. It is most suitable to implementalgorithmic DACs using a switched-capacitor (SC) technique; however,other techniques such as switched-current (SI) can also be used.

FIG. 2A illustrates a SC quasi-passive pipelined DAC (QPPDAC),represented generally by the numeral 10 that is described below.(Originally, SC pipelined DACs used an operational amplifier (op amp) ineach stage for performing the required operations; however, this madethe DAC very expensive.) The DAC is referred to as quasi-passive becauseno op amps are used for performing the required operations. Rather, theDAC essentially comprises capacitors and switches.

The QPPDAC circuit 10 includes a series of stages 12. Each stage 12comprises a capacitor 14 and several switches. A first plate (hereinreferred to as the bottom plate for illustrative purposes only) of thecapacitor 14 is coupled to ground. A second plate (herein referred to asthe top plate for illustrative purposes only) of the capacitor 14 iscoupled to a reference voltage V_(ref) via a first switch 16 and toground via a second switch 18. The top plate of the capacitor 14 is alsocoupled to the top plate of the capacitor in a previous stage via athird switch 20. For the first stage 12 a, there is no previous stagefor the top plate of the capacitor 14 to be coupled. Instead, the topplate of the capacitor 14 is coupled via the third switch 20 to the topplate of an initialization capacitor 22, and an initialization switch24. The initialization capacitor 22 has the same capacitance as theremaining capacitors 14. Both the bottom plate of the initializationcapacitor 22 and the other end of the initialization switch 24 arecoupled to ground. For the final stage 12 f, the capacitor 14 f isfurther coupled to an output stage such as sample and hold (not shown).

FIG. 2B shows a timing diagram for the QPPDAC. The QPPDAC uses athree-phase clock for timing. The clock phases run continuously; thatis, no reset cycle or the like is necessary, and a portion of a newdigital input word is taken in every clock cycle. Also, the phases arestaggered in time and do not overlap. Therefore, the DAC can operate on(N div 3) words at the same time, where N is the number of resolutionbits of the DAC and the portion of the word taken in is three (3) bitsin size.

FIG. 3 provides an illustrative example as to how the bits are inputinto the QPPDAC, represented generally by the numeral 30. In thisexample, N=9, so three numbers can be converted at a time. In a firstclock cycle, three bits from each of three words are input to the DAC32. These bits are the least significant bits (LSB) of word 3, themiddle 3 bits of word 2, and the most significant bits (MSB) of word 1.The less significant bits of word 1 and word 2 have already beenconverted in previous clock cycles. In the next clock cycle, the middlethree bits of word 3, the MSB of word 2, and the LSB of a new word, word4, are converted. Lastly, in the next clock cycle, the MSB of word 3,the middle three bits of word four, and the LSB of a new word, word 5,are converted. Therefore, after 3 clock cycles, an entire 9-bit word isconverted.

Referring once again to FIG. 2A, b_(j)[k] represents the j-th bit of thek-th digital input word. The conversion process for each word beginswith the LSB. Depending on the bit value, either the first switch 16 a(S_(0,1)) or the second switch 18 a (S_(0,2)) is closed during the firstphase of the clock cycle, φ₁. If the first switch 16 a is closed, C₀ ischarged to V_(ref). If the second switch 18 a is closed, C₀ is grounded.Therefore, the voltage at C₀ can be represented as b₀[m]V_(ref), whereb₀ is 1 or 0. At the same time, the initialization switch 24 is closedand the initialization capacitor 22 is discharged to ground. The thirdswitch 20 a remains open and closes only in the following clock phase.

In the second phase, φ₂, of the same clock cycle, the first switch 16 aand second switch 18 a in the first stage 12 a are opened and the thirdswitch 20 a closes. C₀ shares its charge with the initializationcapacitor 22 through the third switch 20 a. Since all the capacitors arematched, the voltage at C₀ is equal to:

V _(C) ₀ =(b ₀ [m]V _(ref))/2

During the same phase of the same clock cycle φ₂, C₁ is charged tob₁[m]V_(ref), where b₁ is 1 or 0.

In the third phase, φ₃, of the same clock cycle, the third switch 20 ain the first stage 12 a opens. Also, the first switch 16 b and thesecond switch 18 b in the second stage 12 b are opened and the thirdswitch 20 b closes. Therefore, the voltage across C₁ and C₀ is shared.Again, since the capacitors are matched, the voltage will divide equallyacross C₁ and C₀. Therefore, at the end of the third phase of the clockcycle, φ₃, the voltage across C₁ is:$V_{C_{1}} = {{\frac{1}{2}{b_{1}\lbrack m\rbrack}V_{ref}} + {\frac{1}{4}{b_{0}\lbrack m\rbrack}V_{ref}}}$

At the same time, that is during φ₃ of the same clock cycle, C₂ ischarged to b₂[m]V_(ref), where b₂ is 0 or 1.

The next phase is the first phase, φ₁, of the next clock cycle. Thefirst three stages behave as described above. The fourth stage 12 dcontinues to convert the same word. The third switch 20 b in the secondstage 12 b opens. Also, the first 16 c and second 18 c switches in thethird stage 12 c are opened and the third switch 20 c closes. Therefore,the voltage across C₂ and C₁ is shared. Again, since the capacitors arematched, the voltage will divide equally across C₂ and C₁. Therefore, atthe end of the first phase, φ₁, of the next clock cycle, the voltageacross C₂ is:$V_{C_{2}} = {{\frac{1}{2}{b_{2}\lbrack m\rbrack}V_{ref}} + {\frac{1}{4}{b_{1}\lbrack m\rbrack}V_{ref}} + {\frac{1}{8}{b_{0}\lbrack m\rbrack}V_{ref}}}$

At the same time, that is during φ₁ of the same clock cycle, C₃ ischarged to b₃[m]V_(ref) where b₃ is 0 or 1.

The digital input bits are properly delayed for ensuring that they areprocessed at the correct time. The DAC continues in a similar fashionuntil a charge is accumulated on the capacitor 14 in the last stage. Atthis point the accumulated charge is an analog representation of thedigital word input. Due to the pipelined architecture of the system, thethroughput of the DAC is one word per clock cycle.

However, this architecture for a QPPDAC suffers from parasiticcapacitance. The parasitic capacitance is due to several factors,including the reverse biased junction capacitance of the switches andany stray metal-to-metal or metal-to-substrate capacitance that couldhave been introduced in the manufacturing process. This parasitic, orstray, capacitance brings stray charge into the conversion operation.

The stray charge in the system is undesirable for two reasons. The firstreason is that the stray charge can lead to a gain error. Since thevoltage on a capacitor is proportional to the charge on the capacitor,any stray charge will affect voltage and will lead to inaccurateresults. The second undesirable affect of the stray capacitance is thatit is typically non-linear. Non-linearity of the capacitors makes theoutput voltage a non-linear function of the input, again distorting theresults. The problem of non-linearity is more serious for high-speedDACs, where large switches (with large junction capacitance) are usedfor shorter charge and discharge times.

Another shortcoming of the QPPDAC is that its largest differentialnon-linearity (DNL) is at the midrange. FIG. 4 illustrates this problem.This large DNL is caused by capacitor mismatch, which is inevitable inthe manufacturing process. In general, a mismatch between any of theequivalent capacitors creates conversion non-linearity.

It is an object of the present invention to obviate or mitigate at leastsome of the disadvantages mentioned above.

BRIEF SUMMARY OF THE INVENTION

In accordance with an aspect of the present invention, there is provideda pipelined digital-to-analog converter (DAC) for converting a digitalinput to an analog output. The pipelined DAC has a plurality of stages.A first of the plurality of stages is coupled to an initializationcapacitor and ground. A remainder of the plurality of stages is coupledto a previous stage. Each of said plurality of stages includes acapacitor, a first switch and a second switch. The capacitor has a firstand second plate and receives a charge at the first plate in accordancewith an associated bit of the digital input. The first switch couplesthe first plate of the capacitor to ground when the capacitor is notreceiving the charge. The second switch couples the second plate of thecapacitor to ground when the capacitor is receiving the charge. Couplingthe capacitor to ground reduces the effect of stray capacitance in thepipelined DAC.

In accordance with a further aspect of the invention, there is provideda DAC for converting a digital input to an analog output. The DACincludes a first DAC circuit, a second DAC circuit, and a combiner. Thefirst DAC circuit is coupled to the digital input and a sign of thedigital input. A reference voltage to the first DAC circuit is positiveif the digital input is positive and negative if the digital input isnegative. The second DAC circuit is coupled to the digital input and aninverse of the sign of the digital input. A reference voltage to thesecond DAC circuit is positive if the digital input is negative andnegative if the digital input is positive. A combiner subtracts theoutput of said second DAC from the output of the first DAC.

In accordance with yet another aspect of the invention, there isprovided a DAC for converting a digital input to an analog output. TheDAC is coupled to a positive reference voltage if the digital input ispositive and a negative reference voltage if the digital input isnegative, thereby doubling the DAC's output range and moving a largedifferential non-linearity from a midpoint of the output range.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will now be described by way of example only withreference to the following drawings in which:

FIG. 1 is a flow diagram describing an algorithm for a digital to analogconverter (prior art);

FIG. 2A is a schematic diagram of a quasi-passive pipelined digital toanalog converter (DAC) (prior art);

FIG. 2B is a timing diagram for a clock to be used in the DAC shown inFIG. 2A (prior art);

FIG. 3 is a block diagram illustrating the flow of input into the DACshown in FIG. 2A (prior art);

FIG. 4 is a graph illustrating the position of the largest differentialnon-linearity of the DAC shown in FIG. 2A (prior art);

FIGS. 5A-5C are respectively a schematic diagram, a timing diagram, anda schematic diagram of a quasi-passive pipelined DAC in accordance withan embodiment of the invention;

FIG. 6 is a schematic diagram of a first stage of a sample and holdcircuit;

FIG. 7 is a schematic diagram of a bipolar quasi-passive pipelined DAC;

FIG. 8 is a graph illustrating the position of the largest differentialnon-linearity of the DAC shown in FIG. 7;

FIG. 9 is a schematic diagram of a differential bipolar quasi-passivepipelined DAC;

FIG. 10A is a schematic diagram of a second stage of a sample and holdcircuit;

FIG. 10B is a timing diagram for a clock to be used in the SH circuitshown in FIG. 10A;

FIG. 11 is a schematic diagram of a pipelined DAC with a pair ofparallel final stages;

FIG. 12 is a schematic diagram of a cyclic DAC with a positive and anegative reference voltage; and

FIG. 13 is a schematic diagram of a differential bipolar cyclic DAC.

DETAILED DESCRIPTION OF THE INVENTION

For convenience, like numerals in the description refer to likestructures in the drawings.

Referring to FIG. 5A, a QPPDAC circuit is represented generally by thenumeral 50. The circuit 50 behaves in a similar fashion to the circuit20 illustrated in FIG. 2A; however, it is arranged for minimizing theeffects of stray capacitance. The circuit 50 includes several stages 52.Each stage comprises a capacitor 54 and several switches. A top plate ofthe capacitor 54 is coupled to ground via a first switch 56. The topplate of the capacitor is further coupled to the previous stage via asecond switch 58. A bottom plate of the capacitor 54 is coupled to thereference voltage V_(ref) via a third switch 60 and coupled to groundvia a fourth switch 62. The bottom plate is further coupled to groundvia a fifth switch 64.

For the first stage 52 a, there is no previous stage for the top plateof the capacitor 54 a to be coupled. Rather, the top plate of thecapacitor 54 a is coupled via the second switch 58 a to the top plate ofan initialization capacitor 66 and to an initialization switch 68. Theinitialization capacitor 66 has the same capacitance as the othercapacitors 54. Both the bottom plate of the initialization capacitor 66and the other end of the initialization switch 68 are coupled to ground.For the final stage 52 f, the capacitor 54 f is further coupled to anoutput stage such as sample and hold (not shown). Referring to FIG. 5B,a three-phase clock is implemented for the timing of the circuit 50, asin the prior art.

Implementing the QPPDAC in the above manner removes a majority of theeffect of stray capacitance. For example, charging the capacitor 54 a inthe first stage 52 a to V_(ref) (assuming bit b₀[m] is a 1) is describedas follows.

FIG. 5C shows an exploded view of the first stage 52 a of the circuit50. The figure includes schematic representations of the parasitic(stray) capacitance. The capacitor 54 a is charged during the firstphase, φ₁, of each clock cycle. Therefore, the first switch 56 a isclosed and the top plate of the capacitor 54 a is grounded. The straycapacitance 70 associated with the top plate of the capacitor 54 a iseffectively removed since both “plates” of the parasitic capacitance 70are coupled to ground.

While the top plate is grounded, the bottom plate is charged with acharge equal to:

q=C ₀ V _(ref)

When the clock enters the second phase φ₂, the first switch 56 a isopened, as is the switch 60 a providing the reference voltage. Duringφ₂, the bottom plate is grounded via the switch 64 a. The parasiticcapacitance 72 associated with the bottom plate of the capacitor 54 ais, therefore, effectively removed since both “plates” of the parasiticcapacitance are coupled to ground. Since the charge on the capacitor 54a remains the same, so must the voltage across it. Therefore, when thebottom plate is grounded, the voltage is transferred to the top plate.The switch 58 a connecting the first stage 52 a to the initializationcapacitor 66 is closed and the voltage across the capacitor 54 a isshared. The circuit continues to work in the same manner as described inthe prior art using the architecture described in the present embodimentof the invention until the charge on the final capacitor represents ananalog conversion of a digital input.

There is still, however, an issue with non-linearity. Although the gainerror is improved by grounding the top plate while the capacitors arecharging, there is still a non-linearity introduced by the switches thatcannot be avoided. The non-linearity, however, can be removed after thelast stage 54 f of the DAC, as described below.

Referring to FIG. 6, a first stage of a sample and hold (SH) circuit isillustrated generally by numeral 80. The first stage of the SH circuit80 comprises an inverting amplifier 82, a linear SH capacitor 84, afirst SH switch 86 and a second SH switch 88. The SH capacitor 84 iscoupled to the amplifier in a negative feedback configuration. The firstSH switch 86 couples the input of the amplifier 82 to the top plate ofthe capacitor 54 f in the last stage 52 f of the DAC. The second SHswitch 88 couples the output of the amplifier 82 to the bottom plate ofthe capacitor 54 f in the last stage 52 f of the DAC. Non-linearcapacitance associated with the system is represented graphically as acapacitor 90.

In the embodiment illustrated in FIG. 6, the resolution of the DACmodulus the number of bits input at a time is equal to one. Therefore,the capacitor 54 f in last stage 52 f of the DAC is charged during thefirst phase φ₁ of the clock cycle. Similarly, if the resolution of theDAC modulus the number of bits input at a time was equal to two, thecapacitor in the last stage of the DAC would be charged during thesecond phase φ₂ of the clock cycle. Since the number of bits input at atime is equal to three for the present embodiment, the last alternativeoccurs when the resolution of the DAC modulus the number of bits inputat a time is equal to 0. In this case, the capacitor in the last stageof the DAC would be charged during the third phase φ₃ of the clockcycle.

For any of the above described cases, the SH switches 86 and 88 bothclose two phases after the capacitor is charged. In the embodimentillustrated in FIG. 6, the SH switches 86 and 88 close during the thirdphase, φ₃. This allows the capacitor to charge to the value of the n-thbit during the first phase, and allows the previous n−1 bits to be addedto the n-th bit in the second phase. During the third phase φ₃, the SHswitches 86 and 88 are closed. The input to the amplifier 82 is atanalog ground and therefore forces the top plate of the capacitor 54 fin the last stage 52 f to ground. Therefore, the non-linear capacitance90 is effectively removed, since both the top “plate” and the bottom“plate” are grounded. Since all of the other switches are open, thecharge associated with the capacitor 54 f on the final stage is sharedwith the SH capacitor 84. If the capacitors 54 f and 84 are matched andthere is no charge already on the SH capacitor 84, then they will sharethe charge equally. Since both capacitors are linear, the output of theDAC will be linear.

Referring to FIG. 10A, a second stage of the sample and hold (SH)circuit is illustrated generally by numeral 200. The second stage of theSH circuit 200 comprises an amplifier 82, a sample capacitor C_(S), ahold capacitor C_(H), and four SH switches S₁, S₂, S₃, and S₄. One endof sample capacitor C_(S) is coupled the output of the first stage SHcircuit 80 via the first switch S₁ and to the output of the amplifiervia the third switch S₃. The other end of the sample capacitor C_(S) iscoupled to the input of the amplifier 82 via the fourth switch S₄ and toground via the second switch S₂. The hold capacitor C_(H) is coupled tothe amplifier 82 in a negative feedback configuration.

Referring to FIG. 10B, the timing for the switches in FIG. 10A isillustrated. The first and second switches S₁ and S₂ are closed first,simultaneously. This charges the sample capacitor C_(S) to the inputvoltage. The first and second switches S₁ and S₂ are then opened and thethird and fourth switches S₃ and S₄ are closed. This transfers the inputvoltage to the hold capacitor C_(H). The second stage of the SH circuit200 provides continuous time linearity, that is, linearity duringtransients. While a specific SH circuit is described above, the DAC maybe implemented using other SH circuits that are either proprietary orknown in the art.

The DAC, however, still has its largest differential non-linearity (DNL)at the middle of its range. The DNL can be reduced and moved away fromthat point by a technique referred to as bipolar conversion.

FIG. 7 illustrates the DAC previously described, further amended forallowing bipolar conversion, represented generally by the numeral 190.This DAC circuit 190 behaves in a similar fashion as the previouslydescribed circuit illustrated in FIG. 5A. However, the reference voltageV_(ref) that is applied depends on the sign of the input word that isbeing converted. If the input word is negative, then a negative voltageis applied. If the input word is positive, then a positive voltage isapplied. In FIG. 7, the sign of the input is represented as s[m], wheres[m]=±1. The sign of the input may be represented with a sign bit or intwo's complement notation. There are several effective methods ofconverting between the two formats that are known to a person skilled inthe art. The magnitude of the digital input determines the magnitude ofthe analog output. For unipolar conversion, the DAC ranges from 0 to amaximum in a positive direction on both axes. For bipolar conversion,the DAC ranges from a maximum in a negative direction to a maximum inthe positive direction on both axes.

There are two advantages in using this architecture. First, the majorDNL error is moved away from the midpoint to the ¼ and ¾ range points.Secondly, since the output range is effectively doubled, thenon-linearity loses its significance by one bit. These facts are betterillustrated in the linearity plots shown in FIG. 8. While thediscontinuities have maintained their sizes, one extra bit of resolutionis obtained due to the doubled output range. The fact that the converteris most linear at the midpoint makes the dynamic range of the DACvirtually independent of its linearity. This is a significant advantagefor this DAC in many practical applications such as audio and voice.

However, there is a difficulty with the implementation of a bipolar DAC.A mismatch between the positive and negative voltages can causesignificant non-linearity.

FIG. 9 illustrates a differential architecture, represented generally bythe numeral 90, that is used for avoiding this issue as well asimproving the noise immunity of a DAC in a system. The differentialarchitecture 90 includes a positive bipolar pipelined DAC circuit 92, anegative bipolar pipelined DAC circuit 94, a combiner 96, and a sampleand hold circuit 98. Each DAC circuit 92 and 94 has a first input, asecond input, and an output. The output of each DAC circuit 92 and 94 isconnected to the combiner 96. The combiner 96 is connected to the sampleand hold circuit 98.

The first input for each DAC is used for receiving the digital input andthe second input for each DAC is used for the sign of the digital input.The negative DAC circuit 94 is virtually a mirror image of the positiveDAC circuit 92. While they share the same digital input, they useopposite reference voltages. A signal to be input to the sample and holdcircuit 98 is obtained by subtracting the output of the negative DACcircuit 94 from the output of the positive DAC circuit 92 in thecombiner 96. The sample and hold circuit is preferably a differentialcircuit itself.

The differential DAC can therefore virtually cancel the referencevoltage mismatch by averaging them out. Although this is clearintuitively, a mathematical derivation helps to quantify it. Let theinherent gain of the plus 92 and minus 94 sides be G_(p) and G_(m)respectively. Ideally, G_(p)=G_(m)=1, but due to capacitor mismatchesthese gains may have slight errors. The actual gain (slope) of the plusside 92 and the minus side 94 for a digital input with a positive signis then G_(p)V_(ref+) and G_(m)V_(ref−) respectively. The overall slopeof the converter, after sample and hold 98, for positive digital inputscan be written as:

S _(p) =G _(p) V _(ref+) −G _(m) V _(ref−)

Similarly, the negative slope is:

S _(n) =G _(p) V _(ref−) −G _(m) V _(ref+)

Ideally, S_(p)=−S_(n), and no distortion is caused by slope mismatch.The exact slope mismatch is:

ΔS=S _(p) +S _(n)=(G _(p) −G _(m))(V _(ref+) +V _(ref −))

This mismatch is less than the single-ended mismatch ofV_(ref+)+V_(ref−) by a factor of G_(p)−G_(m).

Another advantage of the differential architecture for the DAC is thereduction of capacitor non-linearity error. Capacitor non-linearity canarise from penetrations of an electric field of the capacitor into theplates. This non-linearity affects the integral linearity of theconverter.

Generally, the pipeline stages settle faster than the SH circuit.Therefore, to avoid the speed of the SH circuit becoming a bottleneck,an additional stage is added in parallel with the last stage.

Referring to FIG. 11, this embodiment of the invention is illustratedgenerally by numeral 250. The stages 252 and 254 are multiplexed betweenthe DAC and the SH circuit. While one of the stages is participating inthe digital to analog conversion, the other is transferring charge tothe SH. This allows the SH circuit to operate as slow as half the speedof the DAC circuit without constraining the overall conversion speed.

While the embodiments described above refer to the pipelineimplementation of the DAC, the ideas can just as effectively beimplemented for a cyclic DAC. Referring to FIG. 12, a cyclic DAC isprovided with a positive and negative voltage, which has the sameeffects as described for the pipelined DAC. Further, referring to FIG.13, a cyclic DAC with a positive reference voltage and a cyclic DAC witha negative reference voltage are coupled in parallel. Again, this hasthe same effects as described for the pipelined DAC.

While the pipelined DAC produces a new output on every clock cycle, thecyclic DAC requires a number of clock cycles for a conversion. The SHstage circuit of the cyclic DAC is approximately 3 times slower than theswitch and capacitors in the transfer of change. Since the number ofconversion bits is typically much larger than 3, the same SH stagecircuit can be shared by multiple cyclic DAC circuits. Therefore, a bankof cyclic DACs may be implemented that delivers conversion rates betweenthose of a single cyclic DAC and a pipelined DAC.

While the invention has been described in connection with a specificembodiment thereof and in a specific use, various modifications thereofwill occur to those skilled in the art without departing from the spiritof the invention.

The terms and expressions which have been employed in the specificationare used as terms of description and not of limitations, there is nointention in the use of such terms and expressions to exclude anyequivalents of the features shown and described or portions thereof, butit is recognized that various modifications are possible within thescope of the invention. The present invention is intended to be definedaccording to the following claims and their equivalents.

What is claimed is:
 1. A pipelined digital-to-analog converter (DAC) for converting a digital input to an analog output, said pipelined DAC comprising: a plurality of stages, a first of said plurality of stages being coupled to an initialization capacitor and ground, each of a remainder of said plurality of stages being respectively coupled to a previous stage, wherein each of said plurality of stages includes: a capacitor having a first plate and a second plate, said capacitor receiving a charge at said first plate in accordance with an associated bit of said digital input; a first switch that selectively couples said first plate of said capacitor to ground when said capacitor is not receiving said charge; and a second switch that selectively couples said second plate of said capacitor to ground when said capacitor is receiving said charge, wherein coupling said capacitor to ground reduces an effect of stray capacitance in said pipelined DAC.
 2. The pipelined DAC of claim 1, wherein each of said remainder of said plurality of stages are respectively coupled to said previous stage by a third switch coupled between said second plate of said capacitor and a second plate of a corresponding capacitor in said previous stage.
 3. The pipelined DAC of claim 1, wherein said first plate is coupled to a reference voltage if said associated bit of said digital input is equal to one and coupled to ground if said associated bit of said digital input is equal to zero.
 4. The pipelined DAC of claim 3, wherein said reference voltage is positive if said digital input is positive and said reference voltage is negative if said digital input is negative.
 5. The pipelined DAC of claim 1, further comprising a first sample and hold (SH) circuit, wherein said first SH circuit comprises: a first amplifier having an input and an output, wherein said input is coupled to said second plate of said capacitor in a last stage of said plurality of stages via a first SH switch, and wherein said output is coupled to said first plate of said capacitor in said last stage via a second SH switch; and a first SH capacitor coupled to said first amplifier in a negative feedback configuration, wherein said charge is transferred from said capacitor in said last stage to said first SH capacitor in a linear fashion for providing a linear output.
 6. The pipelined DAC of claim 5, wherein said last stage comprises two parallel stages for reducing a bottleneck at said first SH circuit, said first SH circuit multiplexing between each of said two parallel stages.
 7. The pipelined DAC of claim 5, further comprising a second SH circuit, wherein said second SH circuit comprises: a second SH capacitor having a first plate and a second plate, said first plate being coupled to an output from said first sample and hold circuit via a third SH switch and said second plate being coupled to ground via fourth SH switch; a second amplifier having an input thereof coupled to said second plate of said second SH capacitor via a fifth SH switch and an output thereof coupled to said first plate of said second SH capacitor via a sixth SH switch; and a hold capacitor coupled to said second amplifier in a negative feedback configuration.
 8. The pipelined DAC of claim 1, further comprising a second pipelined DAC operating in parallel with said pipelined DAC, wherein said pipelined DAC is coupled to said digital input and a sign of said digital input, wherein said second pipelined DAC is coupled to said digital input and an inverse of said sign of said digital input, and wherein an output of said second pipelined DAC is subtracted from an output of said first pipelined DAC.
 9. The pipelined DAC of defined in claim 8, wherein a difference resulting from said subtraction is input to a sample and hold circuit.
 10. A pipelined digital-to-analog converter (DAC) for converting a digital input to an analog output, said pipelined DAC comprising: a first plurality of stages, coupled to said digital input and a sign of said digital input, wherein a reference voltage to said first plurality of stages is positive if said digital input is positive and negative if said digital input is negative, wherein a first of said first plurality of stages is coupled to an initialization capacitor and ground, and wherein each of a remainder of said first plurality of stages is respectively coupled to a previous stage; a second plurality of stages, coupled to said digital input and an inverse of said sign of said digital input, wherein a reference voltage to said second plurality of stages is positive if said digital input is negative and negative if said digital input is positive, wherein a first of said second plurality of stages is coupled to an initialization capacitor and ground, and wherein each of a remainder of said second plurality of stages is respectively coupled to a previous stage; and a combiner for subtracting an output of said second plurality of stages from an output of said first plurality of stages, wherein each of said first and second plurality of stages includes: a capacitor having a first plate and a second plate, said capacitor receiving a charge at said first plate in accordance with an associated bit of said digital input; a first switch that selectively couples said first plate of said capacitor to ground when said capacitor is not receiving said charge; and a second switch that selectively couples said second plate of said capacitor to ground when said capacitor is receiving said charge, wherein coupling said capacitor to ground reduces an effect of stray capacitance in said pipelined DAC. 